Scanning arrangement in a telephone switching system

ABSTRACT

In a switching system, a scanning arrangement is provided to interrogate a plurality of links interconnecting a plurality of switching stages of the system for determining their busy and idle conditions. The scanning arrangement includes a plurality of diode-gating means responsive to the interrogating signals for applying the busy and idle status signals of the links to the register means of the system wherein each of said diode-gating means is coupled to the scanning means and the register means and to a corresponding one of the plurality of links. Each of the diode gating means includes a DC potential source, a junction, first resistor coupling the DC potential source to the junction, second resistor coupling the junction to the corresponding link, a capacitor coupling the scanning means to the junction, and a diode being coupled to the junction and being poled to change from a nonconductive to conductive state in response to the change in the condition of the corresponding link from an idle to busy condition. The system is also provided with a plurality of biasing means, each means establishing a predetermined common bias potential level at the output of a selected number of the plurality of the diode-gating means.

United States Patent inventors Appl. No. Filed Patented AssigneePriority SCANNING ARRANGEMENT IN A TELEPHONE SWITCHING SYSTEM 6 Claims,4 Drawing Figs.

US. Cl 179/18, 17911 (GF) Int. Cl H04q 3/48 Field of Search 179/ 1 8(BT), 18.7 (YA) References Cited UNITED STATES PATENTS 3,430,000 2/ l969 Rohrig 179/18(BT) 3,414,678 12/1968 Hackenberg 179/18(BT) 5/1966 M01etal 179/18(BT) 2,967,212 l/l96l Burston etal ABSTRACT: In a switchingsystem, a scanning arrangement is provided to interrogate a plurality oflinks interconnecting a plurality of switching stages of the system fordetermining their busy and idle conditions. The scanning arrangementincludes a plurality of diode-gating means responsive to theinterrogating signals for applying the busy and idle status signals ofthe links to the register means of the system wherein each of saiddiode-gating means is coupled to the scanning means and the registermeans and to a corresponding one of the plurality of links. Each of thediode gating means includes a DC potential source, a junction, firstresistor coupling the DC potential source to the junction, secondresistor coupling the junction to the corresponding link, a capacitorcoupling the scanning means to the junction, and a diode being coupledto the junction and being poled to change from a nonconductive toconductive state in response to the change in the condition of thecorresponding link from an idle to busy condition. The system is alsoprovided with a plurality of biasing means, each means establishing apredetermined common bias potential level at the output of a selectednumber of the plurality of the diodegating means.

5W1 rc H/IV 6 NETWORK) PATENTEDAPR SIB?! 315,713,383 same or 3 REGsis'vslsea PATENTED m slam sum: or 3 SCANNING ARRANGEMENT IN A TELEPHONESWITCHING SYSTEM BACKGROUND OF THE INVENTION 1. Field of the InventionThe present invention relates to a scanning arrangement in atelephone-switching system for determining the free or busy conditionsof the links interconnecting the switching stages of the system, ingeneral, and more particularly, to an improved scanning arrangementhaving gating means coupled to the links for testing their free or busyconditions.

2. Description of the Prior Art 7 In accordance with the prior art suchas British Pat. No. 981,908, a plurality of links interconnecting aplurality of switching stages are scanned by a scanning arrangementhaving a plurality of gating circuits respectively coupled to the links.According to the patent, the gating circuits include magnetic coreswhich are arranged with discrete electrical components. Such asarrangement has been found rather complex and expensive. 1

SUMMARY OF THE INVENTION It is an object of the present invention toprovide an improved scanning arrangement which overcomes theaforementioried shortcomings of the prior art.

In accordance with the invention, there is provided a scanningarrangement in which each of the gating circuits includes first andsecond resistances, a capacitance and a diode, each with a commonterminal, the other terminals of said first and second resistances beingconnected to the associated link and to a first DC potentialrespectively, the other terminal of said diode, which constitutes theoutput terminal of said gate, being coupled to a second DC potentialwhile the other terminal of said capacitance is connected to said pulsesource, and that the state of conductivity of said diode is reversedwhen an interrogation pulse is applied to said gate and simultaneouslythe associated link is in a predetermined one of its two states;

According to another characteristic of the present testing arrangement,the ratio of said first and second resistances of each gate is chosen toapproximatively obtain the same predetermined potential at their commonterminal when the associated link is busy and irrespective of the linktype when each type is characterized by a different value of busypotential.

The present invention also relates to a matrix arrangement in which acolumn circuit is coupled to a plurality of row conductors viarespective unidirectional impedances.

Such a matrix arrangement is well known in the art but presents arelatively high leakage capacitance. Therefore it is a further object ofthe present invention to provide a matrix arrangement of the above typewhich does not present the mentioned drawback.

The present matrix arrangement is characterized by the fact that saidcolumn circuit includes m column conductors each associated with acorresponding group of said row conductors and that said m columnconductors are connected in common to the input of an output amplifiervia m respective second unidirectional impedances.

The above mentioned and other objects and features of the invention willbecome more apparent and the invention itself will be best understood byreferring to the following description of embodiments taken inconjunction with the accompanying drawings in which:

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 shows a testing arrangement inaccordance with the invention, for testing the free and busy states ofthe links of a telephone exchange switching network;

FIG. 2 shows in detail part of a column circuit of the arrangement ofFIG. I;

FIG. 3 schematically represents a path between a subscribers linecircuit and a junctor circuit in the switching network of FIG. I, aswell as the marking switches associated thereto;

FIG. 4 shows some marking pulse waveforms involved in the establishmentof the path of FIG. 3.

DETAILED DESCRIPTION OF THE INVENTION Referring to FIG. I, the testingarrangement shown therein comprises a matrix. The matrix is made of anarray of crossover points formed by n planes each having m rows, whereeach of the m rows are crossed by k columns and where m, n, and k areinteger numbers. The matrix is thus a three-dimensional one formed bycrossover points made by k, by m, by n intersecting crossover points.The m by n row wires of the matrix are divided in m groups ofn row wiresX,, X,, to X,,,,

X,,,,, and the row wires of each of these m groups are coupled to the kmatrix outputs P, to P via k corresponding column wires Y,, Y,,, to Y,,Y,,,,, and associated decoupling diodes D,, D to D,,,, D,,,,, The freeends of the row wires X,, to X,,,,, of the above matrix are connected torespective ones of the [inn outputs of a scanning circuit SC. Each ofthe k outputs P, to P of a matrix is connected to a corresponding inputof a register circuit REG via the cascaded connection of a bufferamplifier BA, to BA, and a column ainplifier A, to A,, respectively, thecolumn amplifiers A, to A and register REG being common to the matrix ofthe testing arrangement. The crosspoints of the row wires X,, to X,,,,,and column wires Y,, to Y,,,,, are each constituted by a gating circuitcomprising four elements which have a common terminal: a capacitor C,, adiode W, and two resistors R, and R The free end of capacitor C, and thecathode of diode W, are connected to their associated row and columnwires respectively, whereas the free ends of resistors R, and R areconnected to an associated link (not shown) of a switching network SNand to a source of positive DC potential E, respectively.

Each of the column wires Y,, to Y,,,,, of a matrix is further connectedto a source E of positive DC potential via a respective seriesconnection of a diode W and a resistor R (R l ,300 ohms). The matrix ofthe testing arrangement moreover includes an additional row X, whichserves for checking purposes as it will be described later. This row X,is connected to one column wire, e.g. Y,, to Y,,,, out of each of the ksets of m column wires leading to a corresponding matrix output P, andP,,, via a respective crosspoint gating circuit comprising threeelements with a common terminal. The crosspoint gates associated withrow X, each comprise a capacitor C (C C, a diode W and a resistor R,(R5150 kilohms), the free terminals of capacitors C and the cathodes ofdiodes W being connected to row wire X, and to column wires Y,, to Y,,,respectively. The free ends of resistors R are connected to the sourceE, of positive DC potential.

FIG. 2 shows the detailed circuitry of the buffer and column amplifiersBA, and A, respectively (i=1 to k). The buffer amplifier BA, comprisesan NPN transistor Ql mounted in the emitter follower configuration. Thebase of transistor Q, is connected, on the one hand to its emitter via aresistor R and on the other hand directly to the output P, of the matrixassociated with the amplifier BA,. The collector of transistor 0, isconnected to a source E of positive DC potential via a resistor R,,. Theparallel connection of the outputs of the l homologue buffer amplifiersBA, (i=1 to k), which are respectively associated to the matrix of thetesting arrangement, is connected to ground via a resistor R in serieswith the parallel connection of a resistor R and a capacitor C,,resistors R and R and capacitor C, forming part of the common outputamplifier A,. The latter amplifier A, comprises two NPN transistors Qand Q The base of transistor Q, is connected directly to the junction ofresistors R, and R and to its emitter via a diode W.,, the commonconnection of the anode of diode W, and the emitter of transistor Qbeing connected to the source E The collector of transistor Q isconnected to the source E of positive DC potential and to the source Evia a resistor R and a resistor R, respectively and to the base oftransistor Q via a capacitor C The transistor 0;, has its emitterconnected to ground and its base further connected to the source E via aresistor R,,. The collector of transistor O:, which constitutes theoutput of column amplifier A, is connected on the one hand to thel-input of a corresponding bistable device (not shown) of register REGand on the other hand to the source E via a resistor R,

FIG. 3 schematically shows a path between the cutoff relay Car of asubscribers line circuit LC and a junctor circuit JC in the switchingnetwork SN wherein the subscribers line circuits and the junctors areintercoupled through four cascaded switching stages which are themselvesintercoupled via links. The path between the cut off relay Cor and thejunctor circuit LC may be established through these four cascadedswitching stages and more particularly through the four relays Ar, Br,Cr, Dr and their make contacts ar, br, cr, dr included in theseswitching stages respectively. Hereby contact ar interconnects therelays Car and Ar, contract hr the relays Ar and Br, contact cr therelays Br and Cr and contact dr the relays Cr and Dr. The links betweenrelays Ar-Br, Br-Cr and Cr-Dr are referred to as, la, lb, 1c (links -a,-b, -c) respectively. The other ends of relays Dr and Car are connectedto ground via the series connection of a decoupling diode W and the makecontact jr of a relay Jr of the junctor circuit JC, and to a source E,of negative DC potential respectively. The junction point of the cathodeof diode W and relay Dr is connected to the emitter of an NPN switchingtransistor TJ, via the series connection of a resistor R, and the makecontact mr, of a relay Mr (not shown) associated to junctor JC. Thecollector of transistor TJ is connected to a source E of positive DCpotential via a current source I. The junction point of contact ar andrelay Ar (Contact hr and relay Br, contact or and relay Cr, contact drand relay Dr) is connected to the collector of an NPN switchingtransistor TA (TB, TC, TD) via a decoupling diode GA (GB, GC, GD). Theemitters of transistors TA, TB, TC, TD are connected to ground, whereastheir bases ta, tb, tc, td, as well as the base tj of transistor T] areconnected to respective outputs of a path marking circuit (not shown).The relay Jr has one of its two ends connected to ground and its otherend coupled to the source 5., via the make contact mr of the above relayMr. The links la, lb, lc of the above path are connected to threecorresponding resistors R, of the testing arrangement of FIG. 1,previously described.

FIG. 4 is a diagram representing the pulse waveforms ta, lb, tc, td, tj,applied by the above-mentioned path-marking circuit to the correspondingbase electrodes of the switching transistors TA, TB, TD, TJ, during theestablishment of the connection between the line circuit JC. Thefunction of these waveforms will hereinafter be explained together withthe principle of operation of the whole arrangement.

When the above path-marking circuit receives from a central processor(not shown) of the exchange the order to establish the path of FIG. 3,it energizes the above relay Mr associated to the junctor JC. Theenergized relay Mr closes its make contacts mr, and mr,, the closure ofmake contact mr, interconnecting the emitter of transistor TJ andresistor R,., and the closure of make contact mr causing theenergization of relay Jr. At the same time the pulse tj, which has awidth T equal to the marking period of the path, is applied to the basetj of the normally cutoff transistor so that this transistor TJ isswitched to the conductive condition. A positive potential E is thusapplied to the junction point of diode W and relay Dr so that diode W,is blocked. The latter diode decouples the termination of the path LC-JCfrom the ground which is connected thereto via closed contact jr ofrelay Jr. After the start of application of pulse tj, pulses 1d, tc, tf,ta of equal width with respect to each other are consecutively appliedto the corresponding bases of transistors TD, TC, TB, TA, the trailingedge of first applicated pulse td coinciding with the leading edge oflast applicated pulse ta. In this way relays Dr, Cr, Br and Ar areenergized one after another via their associated line circuit LC. At theend of pulse 1], i.e. of the path marking period T, transistor Tj isswitched back to its cutoff condition. Due to transistor TJ beingswitched off and the connection from cathode of diode W, to source tosource E, being established, the latter diode W becomes conductive andthe path LC-.IC is held by the closed make contact jr of relay Jr. Theabove relay Mr which controls relay Jr via contact mr is held operateduntil the end of the busy condition of its associated junctor circuitJC. The release of path LC-JC, established as above, is performed byreleasing this relay Mr. Contact mr, of the released relay Mr breaks theholding path of relay Jr, thus causing the release thereof and hence theopening of its make contact jr. Due to the connection LC-JC being brokenby the opening of contact Jr, relays Cor, Ar, Br, Cr, Dr are released.

It is to be noted that the links la, lb, lc, when in the busy state, areat different potentials with respect to one another, owing to thevoltage drops across their associated relays in cascade. Obviously, theswitching network SN includes other paths interconnecting circuits ofdifferent types of the telephone exchange, e. g. signalling circuits andoutgoing junction circuits etc., but it can be so designed that thelinks of the switching stages of all these paths have busy statepotentials substantially equal to the busy state potentials of the linksla, lb, lc. The ratio of the potentiometer resistances R, and R of eachgate of the testing arrangement of FIG. 1, is chosen in accordance withthe type of the relevant link, i.e. with the busy state potential valueof this link. For instance, for the a type links which have a busy statepotential of about -l 3 volts, the resistances R, and R are equal to 620K. ohms and 240 K. ohms respectively. In this way, for all busy linksand irrespective of their type, the same potential of e.g. 0 volts isobtained at the junction point of the resistances R, and R in each ofthe gates correspondingly associated thereto. When a link of switchingnetwork SN is in the free state, in which both ends of the link arefloating, it is obvious that the potential at the junction point of theresistances R, and R of its associated gate is equal to that of thesource E, positive potential, e.g. +5 volts, connected thereto via theabove resistance R,.

It is to be noted that resistances R, and R are of high value, in orderto ensure a sufficient decoupling between the gating circuits of thetesting arrangement matrices and the switching network SN.

The principle of operation of the testing arrangement of FIGS. 1 and 2is as follows:

In the rest condition of the testing arrangement, all row wires X,, toX,,,,,, as well as row wire X, in the matrix thereof, are at the groundpotential connected thereto via the output resistors (not shown) of theassociated selection gates (not shown) included in the scanning circuitSC. The diodes W, of the gating circuits of the arrangement are in theirblocked condition, since their anodes are at ground potential or at thepositive potential of source E, (+5 volts) depending on their associatedlinks being in their busy or free state respectively, and their cathodesare at the more positive potential of source E e.g. +12 volts, appliedthereto via resistors R and decoupling diodes W associated to eachcolumn Y,, to Y,,,,,. for the same reason diodes W associated with rowX, are in their blocking condition, too. Diodes D,, to D, are blockedsince their anodes are biased at the positive potential of source E, viathe series connections of R, and W, and since their cathodes are alsobiased at the same positive potential E via conductive diodes Wresistors R, and R Transistors Q, and Q are in the cutoff condition,since their base and emitter electrodes are at the same potential,whereas transistors Q, are conductive. Consequently the outputs ofcolumn amplifiers A, and A,, taken at the collectors of the respectivetransistors 0 are substantially at ground potential.

When a path has to be established through the switching stages ofnetwork SN, such as the path of FIG. 3 previously described, theabove-mentioned central processor of the' dition of the links, capableof forming the involved path, is

substantially reduced.

Assuming that row X,, of the matrix of FIG. 1 is interrogated and thatonly the link associated with the crosspoint of row X, and column Y,, isin the busy state, the interrogation pulse applied to row X,, throughscanning circuit SC, will cause the activation of the matrix outputs Pto P, and consequently of the corresponding inputs of register REG viathe associated buffer and column amplifiers BA to BA, and A to A Indeed,the above interrogation pulse, which has an amplitude equal to the DCpotential level of source E e.g. 12 volts, will cause the diodes W, ofall crosspoints of row X,,, except crosspoint X,,/Y,, thereof, to bebrought in the conductive condition since, as aforementioned, thejunction point of the resistors R,, R of a gate associated with a busyor free link is at the ground potential or at a positive potential of E,volts, e.g. +5 volts, respectively. The potential of column Y, does notchange, so that the buffer amplifier BA, and column amplifier A, remainin their rest condition and the corresponding bistable device ofregister REG registers a -bit, i.e. it remains in its O-condition. Thepotential of columns Y, to Y,, is raised from their bias level of Evolts to E +E, volts (12+5 volts), this potential rise causing theblocking of diodes W associated with columns Y, to Y,,, and theconduction of diodes D to D,,,. The above positive potential of E +E,volts is applied via the conductive diodes D to D to the bases of thetransistors Q, of the corresponding buffer amplifiers HA to BA thuscausing the latter to be switched in the conductive condition. Due tothe above transistors Q, being conductive, a current path is establishedfrom source E e.g. +48 volts, to ground via resistor R collector-emitterjunction of transistors Q,, resistors R and parallel connections ofresistors R and capacitors C.,, respectively. The potential at the baseof transistor Q in each of the column amplifiers A to A becomes morepositive than the potential of source E so that diode W, is brought inthe blocking condition and transistor Q becomes conductive. Due to thetransistor O in each of the column amplifiers A to A being switched inthe conductive condition, the potential of its collector is lowered,e.g. from 16 volts In the rest condition to E volts (12 volts) in theconductive condition so that a negative going pulse is applied viacapacitor C to the base of transistor 0,, due to which the lattertransistor is cut off and its collector potential is raised to E volts12 volts). In this way the bistable devices of register REG associatedto the column amplifiers A to A, are set to their 1-condition, whichmeans that the above considered k-l links are in their free state. Theinformation thus registered in register REG, is supplied to the abovecentral processor, r'egister REG is reset to zero and a newinterrogation order 'is given to the scanning circuit SC. Theinterrogation process is continued in the same way as described above,until the central processor obtains the necessary information about thestates of the links which are capable of forming the required path.

It is to be noted that the 1 sets of buffer amplifiers BA,- (i=1 to k)respectively associated with the matrix of the arrangement, serve forlowering the output impedances of the corresponding matrices, in orderto charge quickly the parasitic capacitances of the input connections ofthe column amplifiers A,, which are common to the above 1 matrices.

Resistors R provide a discharge path for the parasitic capacitances oftheir associated columns. These parasitic column capacitances mainlyconstituted by the leakage capacitances of the matrix diodes, aresubstantially reduced, as it will hereinafter be demonstrated, by meansof an appropriate division in groups of rows X,, to X,, of each matrixof the testing arrangement.

Calling C the leakage capacitance of each of the diodes W,

and qC the leakage capacitance of each of the diodes D,, to D,,,,,, qbeing a numerical factor, and assuming that an interrogation pulse isapplied to a row of the matrix of FIG. 1, e.g.

, row X,,, the parasitic capacitance Cp of a column, such as column Y,,may be written as follows when disregarding row X, and diodes W mu l 1+1+1 1 (1) Indeed, column Y,, is charged with the parasitic capacitance(n-l c of the diodes W, of the crosspoints of the nl noninterrogatedrows X,, to X,,, of group X,, to X,,. This parasitic capacitance (n-lCis in parallel, via conductive diode D,,, with the series connection ofthe parasitic capacitance q (m-l C of the m1 blocked diodes D to D,,,,and the parasitic capacitance n (m-l) C of the n (m-l) diodes W,associated with the m-l columns Y to Y,,,,.

With mn constant the parasitic column capacitance Cp can be minimized infunction of n dCp d qn(m1) dn 1+ q+ 1 (2) From the above relation it isderived that Cp is minimum for When mn is large and factor q is close tothe unity, relation (3) gives approximately:

Cp mn Cp m +11. (5)

When integers m and n 2, which is the case for a matrix then,

Cp rr The above analysis clearly shows the advantages offered by thepresent diode matrix arrangement with respect to a conventional one.

The aim of the bias +E volts applied to the columns Y,, to Y,, of thetesting arrangement matrices, via the resistors R (R and diodes Wassociated thereto, is to prevent an interrogation pulse from becomingeffective for a noninterrogated row, when a diode W, pertaining to acrosspoint gate of the latter noninterrogated row is short circuited.Indeed, suppose that an interrogation pulse is applied to row X,,, thatthe link associated with crosspoint X,,/Y,, is in its free state andthat diode W, of crosspoint X,,,JY,, is short circuited. Then, the +5volts pulse variation (E,+E E =+5 volts) appearing on column Y,,, due tothe link associated with crosspoint X,,/Y,, being in its free state,will be transmitted to the noninterrogated row X,,, via short-circuiteddiode W, of crosspoint X,,,/Y,,. This pulse of 5 volts is however ofinsufficient amplitude to cause any of the other diodes W, associatedwith row X,, to be brought in the conductive condition, since a bias ofE =l 2 volts is applied to the cathodes of the latter diodes.

Finally, concerning row X, of matrix of FIG. 1, an interrogation pulseis periodically applied thereto to check the correct operation of bufferamplifiers BA, (i=1 to k) pertaining to the above matrix, as well as thecorrect operation of the common column amplifiers A,.'Asit may readilybe seen, the application of the interrogation pulse of .-H2 volts to rowX,, will cause the activation of all the k matrix outputs P, to P andnormally all k bistables of register REG must be brought in theirl-condition. In this way, most of the possible failures in columnequipments may easily be detected by simple inspection of the content ofregister REG, after the interrogation of row X,. The failures causingthe output stages Q of column amplifiers A to A to be permanently intheir activated condition (+12 volts) are detected by a secondinspection of the content of register REG, when the whole testingarrangement is in its rest condition.

While the principles of the invention have been described above inconnection with specific apparatus, it is to be clearly understood thatthis description is made only by way of example and not as a limitationon the scope of the invention.

We claim: I

1. A telephone switching system which includes scanning means forinterrogating a plurality of links interconnecting a plurality ofswitching stages of the system and for deriving busy and idle statussignals of said plurality of links to be applied to a register means ofthe system, wherein the improvement comprises a plurality ofdiode-gating means responsive to said interrogating signals for applyingsaid busy and idle status signals of said links to said register means,each of said diode-gating means being coupled to said scanning means andsaid register means, and to a corresponding one of said plurality oflinks, each of said diode-gating means including:

a DC potential source;

a junction;

a first resistive means coupling said DC potential source to saidjunction; a second resistive element coupling said junction to saidcorresponding link;

a capacitive element coupling said scanning means to said junction; and

a first diode means being coupled to said junction and being poled tochange from a nonconductive to a conductive state in response to thechange in the condition of said corresponding link from an idle to busycondition.

2. The switching system in accordance with claim 1, including aplurality of biasing means, each means establishing a predeterminedcommon bias potential level at the outputs of a selected number of saidplurality of gating means.

3. The switching system according to claim 2, wherein said plurality oflinksgenerate busy condition signals of different amplitudes, the ratioof said first and said second resistances of each of said plurality ofgating means being chosen so that the potentials at the respectivejunctions are substantially the same irrespective of the differences inthe amplitudes of the busy condition signals.

4. The system in accordance with claim 3, wherein said scanning meansgenerates interrogation pulses each having an amplitude substantiallyequal to said uniform bias potential level.

5. The system in accordance with claim 4, wherein each of said biasingmeans includes a diode poled opposite to said diode means of said gatingmeans and conducting in response to said gating means detecting saidbusy status signal of the corresponding link.

6. The system in accordance with claim 5, wherein said plurality ofgating means are arranged in a crosspoint gating matrix array of rowsand columns, said plurality of biasing means including means forpreventing short circuiting of any one of said diode means fromaffecting other crosspoints.

1. A telephone switching system which includes scanning means forinterrogating a plurality of links interconnecting a plurality ofswitching stages of the system and for deriving busy and idle statussignals of said plurality of links to be applied to a register means ofthe system, wherein the improvement comprises a plurality ofdiode-gating means responsive to said interrogating signals for applyingsaid busy and idle status signals of said links to said register means,each of said diodegating means being coupled to said scanning means andsaid register means, and to a corresponding one of said plurality oflinks, each of said diode-gating means including: a DC potential source;a junction; a first resistive means coupling said DC potential source tosaid junction; a second resistive element coupling said junction to saidcorresponding link; a capacitive element coupling said scanning means tosaid junction; and a first diode means being coupled to said junctionand being poled to change from a nonconductive to a conductive statE inresponse to the change in the condition of said corresponding link froman idle to busy condition.
 2. The switching system in accordance withclaim 1, including a plurality of biasing means, each means establishinga predetermined common bias potential level at the outputs of a selectednumber of said plurality of gating means.
 3. The switching systemaccording to claim 2, wherein said plurality of links generate busycondition signals of different amplitudes, the ratio of said first andsaid second resistances of each of said plurality of gating means beingchosen so that the potentials at the respective junctions aresubstantially the same irrespective of the differences in the amplitudesof the busy condition signals.
 4. The system in accordance with claim 3,wherein said scanning means generates interrogation pulses each havingan amplitude substantially equal to said uniform bias potential level.5. The system in accordance with claim 4, wherein each of said biasingmeans includes a diode poled opposite to said diode means of said gatingmeans and conducting in response to said gating means detecting saidbusy status signal of the corresponding link.
 6. The system inaccordance with claim 5, wherein said plurality of gating means arearranged in a crosspoint gating matrix array of rows and columns, saidplurality of biasing means including means for preventing shortcircuiting of any one of said diode means from affecting othercrosspoints.